1. Field
This disclosure relates generally to semiconductors, and more specifically, to a method for forming a through silicon via (TSV) layout on a semiconductor device.
2. Related Art
The use of through silicon vias (TSVs) allows the routing of signals through the substrate to the backside of a silicon semiconductor die. In some designs, a TSV can greatly reduce the length of conductors and thereby improve signal routing in an integrated circuit. Also, the implementation of TSVs on a semiconductor device can make stacked die arrangements more practical. However, there is a problem with forming a TSV on a semiconductor device that has undergone CMOS (complementary metal-oxide semiconductor) processing. On a CMOS integrated circuit, nitride may be used in various insulating layers, such as etch stop or passivation layers. TSV etching may create recesses in multilayer dielectric film stacks by laterally etching exposed nitride layers causing recesses. Unintentional recessing within or between the various layers of an integrated circuit structure is not desirable because the recess can cause layers above the recess to separate from each other, or delaminate, resulting in increased defectivity, reduced yields, and reliability. Also, the recess may become a void when the via is lined with a dielectric layer because the recess is too deep for the dielectric layer to fill. To reduce the defectivity, layout rules may include exclusion zones around TSVs. The layout rules may require that active circuitry not be formed within an exclusion zone to allow sufficient spacing from the TSVs to prevent the defectivity problem. However, using exclusion zones around TSVs increases the surface area of the integrated circuit and reduces the ability to scale integrate circuits to smaller sizes.
Therefore, what is needed is a methodology that solves the above problems.